The zero is formed up by the output capacitor in series with its ESR. The pole and zero location decides the loop's stability and transient response rate. So in the LDO data set, we can always see there is an output capacitor ESR stable range specified. The reason is output capacitor ESR value decides the zero location. If ESR is too high, the zero moves towards lower frequency, which increase loop bandwidth.

Use designfilt to generate d based on frequency-response specifications. The pole-zero plot is displayed in FVTool . [ vz , vp , vk ] = zplane( d ) returns the zeros (vector vz ), poles (vector vp ), and gain (scalar vk ) corresponding to the digital filter d .

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